The SAA7108E; SAA7109E is a new multi-standard video decoder and encoder chip, offering high quality video input
and TV output processing as required by PC-99 specifications. It enables hardware manufacturers to implement versatile video functions on a significantly reduced printed-circuit board area at very competitive costs.
Separate pins for supply voltages as well as for I2C-bus control and boundary scan test have been provided for the
video encoder and decoder sections to ensure both flexible handling and optimized noise behaviour.
The video encoder is used to encode PC graphics data at maximum 800 × 600 resolution to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and interlacer ensures properly sized and flicker-free TV display as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 800 ´ 600 resolution/60 Hz (PIXCLK < 45 MHz).
The video decoder, a 9-bit video input processor, is a combination of a 2-channel analog pre-processing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC), automatic clamp and gain control, a Clock Generation Circuit (CGC), and a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM).
The decoder includes a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 MHz VBI data bypass. The pure 3.3 V (5 V compatible) CMOS circuit SAA7108E; SAA7109E, consisting of an analog front-end and digital video decoder, a digital video encode
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· Notebook (low-power consumption)· PCMCIA card application· AGP based graphics cards· PC editing· Image processing· Video phone applications· INTERCAST and PC teletext applications· Security applications· Hybrid satellite set-top boxes.
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1.1 Video decoder· Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS)· Two analog preprocessing channels in differential CMOS style for best S/N-performance· Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel· Switchable white peak control· Two built-in analog anti-aliasing filters· Two 9-bit video CMOS Analog-To-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the IPD (Image Port Data) port under I2C-bus control· On-chip clock generator· Line-locked system clock frequencies· Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection· Requires only one crystal (either 24.576 MHz or 32.11 MHz) for all standards· Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards· Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM· User programmable luminance peaking or aperture correction· Cross-colour reduction for NTSC by chrominance comb filtering· PAL delay line for correcting PAL phase errors· Brightness Contrast Saturation (BCS) and hue control on-chip· Two multi functional real-time output pins controlled by I2C-bus· Multi-standard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc.· Standard ITU 656 Y-CB-CR 4 : 2 : 2 format (8-bit) on IPD output bus·
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